›› 2012, Vol. 38 ›› Issue (4): 45-50.doi: 10.3969/j.issn.1674-1579.2012.04.009
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Abstract: A design scheme of the faulttolerant multiprocessor is proposed to improve the reliability of the MPSOC processor based on voting by software and arbitrating by hardware in this paper. The feasibility of the scheme is validated through experiments.
Key words: system on chip, multi processor, triple modular redundancy, fault tolerant
CHEN Chen, YANG Meng-Fei, LIU Hong-Jin. The Design and Verification of Triple Modular Redundancy MPSOC FaultTolerant Processor[J]., 2012, 38(4): 45-50.
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URL: http://journal01.magtech.org.cn/Jwk3_kjkzjs/EN/10.3969/j.issn.1674-1579.2012.04.009
http://journal01.magtech.org.cn/Jwk3_kjkzjs/EN/Y2012/V38/I4/45
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