›› 2012, Vol. 38 ›› Issue (4): 45-50.doi: 10.3969/j.issn.1674-1579.2012.04.009

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The Design and Verification of Triple Modular Redundancy MPSOC FaultTolerant Processor

  

  • Online:2012-08-25 Published:2013-03-12

Abstract: A design scheme of the faulttolerant multiprocessor is proposed to improve the reliability of the MPSOC processor based on voting by software and arbitrating by hardware in this paper. The feasibility of the scheme is validated through experiments.

Key words: system on chip, multi processor, triple modular redundancy, fault tolerant