中国科技核心期刊

中文核心期刊

CSCD来源期刊

空间控制技术与应用 ›› 2020, Vol. 46 ›› Issue (3): 36-.doi: 10.3969/j.issn.1674-1579.2020.03.005

• 论文与报告 • 上一篇    下一篇

专用指令集在基于FPGA的神经网络加速器中的应用#br#

  

  • 出版日期:2020-06-22 发布日期:2020-07-10

Application of Special Command Set in Neural Network#br#  Accelerator Based on FPGA#br#

  • Online:2020-06-22 Published:2020-07-10

摘要: 近年来,表现出极其优越性能的神经网络算法对硬件算力的要求逐渐提高.在一些低功耗场景如星载系统中,拥有可编程重构、高并行等特性的FPGA是神经网络算法较为合适的硬件加速平台.为了解决传统神经网络硬件加速器设计中片内资源消耗大、各功能模块耦合性高等问题,设计实现了一套专用AI指令集并应用在了基于FPGA的神经网络加速器的设计中.文章首先介绍了该指令集的设计方案.整个指令集由指令寄存器、指令解释器、指令转发模块、内存管理单元和多个模块构成.通过该指令集可实现对不同模块的复用,降低模块之间的耦合性.并以YOLOV3Tiny网络模型为例,对比了平铺式和指令控制式两种加速方案的逻辑资源的消耗.验证了应用专用指令集可以减少约50%的FPGA逻辑资源的使用.

关键词: 指令集, 神经网络, FPGA

Abstract:  In recent years, the requirements of hardware computing power for neural network algorithms that showing extremely superior performance have gradually become higher. In some lowpower scenarios such as spaceborne systems, FPGAs with low power consumption and high parallelism are the most suitable hardware acceleration platforms for neural network algorithms. In order to solve the problems of high onchip resource consumption and high coupling of various operation modules in hardware structure design, a set of dedicated instruction set is designed and implemented to the structural design of FPGAbased neural network accelerator. Firstly, the design and application of the instruction set are introduced. The whole system is composed of instruction register, instruction interpreter, instruction forwarding module, memory management unit, and multiple execution modules. The system can realize the multiplexing of different operation modules and reduce the coupling between modules. Afterwards, the YOLOV3Tiny network model is used as an example to compare the onchip resource consumption of two acceleration schemes, tiled and commandcontrolled. It is verified that the application of dedicated instruction set can effectively reduce the use of FPGA onchip resources.
Keywords: command set;neural network;FPGA

Key words: command set, neural network, FPGA