Abstract: In response to the high computational complexity and model intricacy of deep neural network object detection algorithms, as well as the substantial demand for computational power on hardware platforms, a hardware specific accelerator based on Field Programmable Gate Array (FPGA) chips is designed. Employing a collaborative approach between software and hardware, an on chip architecture with high parallelism and deep pipelining is devised. Additionally, the techniques such as model quantization and structural optimization are utilized to optimize the neural network model. Deploying the object detection algorithm of neural networks within the designed accelerator system achieves high data throughput and low power consumption for FPGA based neural network computation, with model precision loss below 1.2%. This provides an effective solution for deploying deep neural network object detection algorithms on low power embedded platforms and can be widely applied in airborne and spaceborne intelligent computing devices

Key words: FPGA, neural network, hardware accelerator, target detection