1]BROOKS D, TIWARI V, MARGARET M. Wattch: a framework for architecturallevel analysis and optimizations[C]//The 27th International Symposium on Computer Architecture. New York: IEEE, 2000:8394.
[2]TIWARI V, MALIK S,WOLFE A. Power analysis of embedded software: a first step towards software power minimization[J]. IEEE Transactions on Very Large Scale Integreation(VLSI) Systems, 1994,2(4):437445.
[3]GANG Q, NAOYUKI K, KIMIYOSHI U, et al. Functionlevel power estimation methodology for microprocessors[C]//The Design Automation Conference. New York: IEEE, 2000:810813.
[4]PARK Y H, SUDEEP P, FADI J K, et al. A multigranularity power modeling methodology for embedded processors[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2011,19(4):668681.
[5]ERIC S, JOHANN L, NATHALIE J, et al. SoftExplorer: estimating and optimizing the power and energy consumption of a c program for dsp applications[J]. EURASIP Journal on Applied Signal Processing, 2005,16(1):26412654.
[6]SANTHOSH K R, RABIE B A, SMAIL N, et al. Fast and accurate hybrid power estimation methodology for embedded systems[C]//Proceedings of Design and Architectures for Signal and Image Processing (DASIP). New York: IEEE, 2011:17.
[7]JOHN L, NATHALIE J, ERIC S, et al. Functional level power analysis: an efficient approach for modeling the power consumption of complex processors[C]//The Design, Automation and Test in Europe Conference and Exhibition (DATE’04). New York: IEEE, 2004: 666667. |