Abstract:  In recent years, the requirements of hardware computing power for neural network algorithms that showing extremely superior performance have gradually become higher. In some lowpower scenarios such as spaceborne systems, FPGAs with low power consumption and high parallelism are the most suitable hardware acceleration platforms for neural network algorithms. In order to solve the problems of high onchip resource consumption and high coupling of various operation modules in hardware structure design, a set of dedicated instruction set is designed and implemented to the structural design of FPGAbased neural network accelerator. Firstly, the design and application of the instruction set are introduced. The whole system is composed of instruction register, instruction interpreter, instruction forwarding module, memory management unit, and multiple execution modules. The system can realize the multiplexing of different operation modules and reduce the coupling between modules. Afterwards, the YOLOV3Tiny network model is used as an example to compare the onchip resource consumption of two acceleration schemes, tiled and commandcontrolled. It is verified that the application of dedicated instruction set can effectively reduce the use of FPGA onchip resources.
Keywords： command set；neural network；FPGA

Key words: command set, neural network, FPGA